Under the stated assumptions the bias currents are $I_B=40 \mu \mathrm{~A}$ (so $I_{D 3}=I_{D 4}= 200 \mu \mathrm{~A}, I_{D 1}=I_{D 2}=160 \mu \mathrm{~A}$ ), input transistor widths were set to $180 \mu \mathrm{~m}$, an achievable input $g_{m 1}$ upper bound $\approx 4 \mathrm{~mA} / \mathrm{V}$ was used giving $f_{t a} \approx 255 \mathrm{MHz}$; the slew rate is $\approx 80 \mathrm{~V} / \mu \mathrm{s}$ (no clamp) and $\approx 124 \mathrm{~V} / \mu \mathrm{s}$ with the clamp transistors active.